The invention pertains to the field of information processing systems and relates to a particular embodiment of processors that can be used in these systems.
Typically, an information processing system comprises a central subsystem that can communicate with one or more peripheral subsystems. The central subsystem is composed of one or more processors connected, for example by a bus, to a central memory and to one or more input/output units. The input/output units enable communication between the central subsystem and the peripheral subsystem.
The function of each processor is to execute program instructions contained in the central memory. To do this, a processor includes means for addressing the memory, in order to access the instructions and data necessary for processing information. To shorten the mean access time to these instructions and data, the processors are typically provided with a cache memory that serves as a buffer between the central memory and the processing circuits of the processor.
For small systems, in modern very large scale integrated technology or VLSI, the processing circuits of the processor can all be integrated into a single integrated circuit, or chip. For less powerful processors, contrarily, despite the steadily increasing scale of integration, the circuits of the same processor must be distributed among a plurality of integrated circuits. To this end, the processor is subdivided into a plurality of functional units, each of which corresponds to one or more integrated circuits. Thus each integrated circuit of the processor can comprise a specialized processing unit, which contributes to executing the set of machine instructions that the processor can execute. Naturally, each processing unit must be capable of communication with the central memory by way of the cache memory. Moreover, depending on the functional format selected, specific links must be provided that enable communication among these units.
Among the set of processing circuits included in the various units of the processor, distinctions are typically made between a command portion, often called a "command block", and a processing portion, generally called the "data path". The command block drives the addressing circuits and the data path as a function of the instructions received. The addressing circuits command the cache memory to drive both the transfer of the instructions and operands to the processing circuits and the transfer of the results processed by these circuits to the cache memory.
In the case of processors having a large instruction set, the microprogramming technique is generally used for the command block. The command block then essentially comprises a hard-wired microsequencer associated with a microprogram memory. As a function of the operating code of the instruction to be executed and of the logic state of the processor, the microsequencer executes an addressing of the microprogram memory, generally upon each cycle. At its output, the memory furnishes microprogram words that trigger the sending of command signals to the various circuits. Naturally, the command block may also include entirely hard-wired circuits, especially for executing certain functions for which faster optimization is desired.
A typical solution for making the microprogrammed command blocks of a processor is to provide a unit specialized for this function. The command block is then contained entirely within this unit, which may be in the form of an integrated circuit, generally associated with one or more external microprogram memories. European Patent Application Serial No. 85 113207.6, published as No. EP-A-17861 on Apr. 23, 1986, and entitled "Distributed Control Store Architecture", may be mentioned as an example of such a command block.
In this version, each processing unit is commanded in centralized fashion in the command block. As a result, each unit contributes at every moment to the execution of the same microinstruction. It has been seen that the various processing units of the processor are equivalent to sharing the set of processor functions.
For example, a first unit will be assigned the addressing function; another unit will be assigned the logical and digital and decimal arithmetic processing functions; a third unit will be assigned the floating point operations. With this type of functional format, the execution of an instruction, that is, of an associated microprogram, generally does not require the simultaneous effective functioning of these three units. For example, if the instruction comprises adding an operand contained in memory to the contents of a register of the processor and arranging the result in this register, its execution includes the following steps:
1) calculation of the real address of the operand from the logical address defined by the instruction; PA1 2) addressing of the memory, loading the operand into the calculation unit, and execution of the operation; PA1 3) writing the result in the register. PA1 the anticipation indication is absent; PA1 the end-of-microprogram indication is present; PA1 the end-of-instruction signal is absent; then the instruction in standby is called "executable" if the end-of-microprogram indication is present while the inhibition circuit is inactive. PA1 the end-of-instruction signal is present; PA1 the unit is in an anticipated state, or the instruction in standby in the unit is the next instruction to be executed; PA1 the instruction in standby is executable; PA1 the anticipation indication is present; PA1 the effective-end-of-instruction signal is absent; PA1 the end-of-microprogram indication is present; PA1 the anticipation indication is absent; PA1 the anticipated state indicator has the second predetermined value.
In this example, it can be seen that only the addressing unit is used during step 1, and only the calculation unit is used during steps 2 and 3. Thus when one unit is working the others are inactive, which does not represent optimal utilization of the equipment.
The object of the invention is accordingly to overcome these disadvantages, by proposing a processor with multiple microprogrammed processing units capable of functioning with maximum autonomy, to enable optimizing the use of these units and in particular to allow pipeline functioning, in which a plurality of units simultaneously execute microprograms for executing different instructions.
However, the absence of centralization of the command block must be compensated for by a mechanism for synchronizing the microprograms of the various units so that they run in an order determined so as to properly perform the precise functions that correspond to the instructions. The solving of this problem was the subject of French Patent Application 89 15776, filed on Nov. 30, 1989, and entitled "Processeur a plusiers unites de traitement microprogrammees" [Processor with Multiple Microprogrammed Processing Units], corresponding to U.S. application Ser. No 07/620,130,filed Nov. 30, 1990.
In this context of a processor with a plurality of microprogrammed units, the implementation of pipeline functioning requires that each unit be capable of detecting the beginning and end of each instruction and determining at any moment whether it can execute its microprogram corresponding to the execution of the following instructions.
With this object, the subject of the invention is a processor for a data processing system including a plurality of microprogrammed processing units, sharing the set of functions of the processor, each unit being assigned to the execution of a subset of functions of the processor, the units being connected to memory means containing the instructions of the programs to be executed and the operands, at least one of the units being a unit for addressing the memory means for obtaining the instructions and the operands, the processor being characterized in that the units include their own command block for the execution of specific microprograms; that each instruction is composed of a plurality of microprograms that can be executed respectively in the units; that the command block of each unit includes means for commanding instructions to trigger the execution of the microprogram of the first instruction waiting; that the last microinstruction of each of the microprograms includes an end-of-microprogram indication; that certain units and in particular the addressing unit include anticipation means and contain microprograms, the last microinstruction of which includes an anticipation indication to signal whether the following instruction to be executed can be anticipated; and that the anticipation means condition the command means to authorize the execution of the microprogram of the instructions in standby when the microinstruction in progress includes the end-of-microprogram and anticipation indications.
It is understood that the anticipation indication must be provided at the time the microprograms are designed, taking into account certain microprogramming rules associated with the operating format selected. For example, if an instruction is completed in a given unit, the last microinstruction of the corresponding microprogram in each unit need not contain the anticipation indicator. In other words, the next instruction is not anticipatable. The same applies for units that are precluded from functioning with anticipation.
To improve performance, it is advantageous to limit the number of cases requiring in advance that the next instruction not be anticipatable.
To this end, and in a preferred embodiment of the invention, the processor is further characterized in that it includes means permitting the units to exchange end-of-microprogram signals in response to the end-of-microprogram indications; that each unit includes an end-of-instruction detection circuit furnishing an end-of-instruction signal as a function of the end-of-microprogram signals; that each unit includes an inhibition circuit which when it is in its active state prevents any modification of the logic state of the unit; and that this inhibition circuit is in particular made active when the following conditions prevail in combination:
In another aspect of embodiment of the invention, the processor is characterized in that each unit provided with anticipation means includes an anticipated state indicator that initially assumes a first predetermined value and for a second predetermined value signals that the instruction in progress in the unit is executed in anticipation, that is, the execution of which has begun before the previous end of instruction; that the units include an effective-end-of-instruction detector circuit furnishing an effective-end-of-instruction signal when the following conditions pertain, in combination:
that the anticipated state indicator is put at the predetermined second value when the following conditions are present in combination:
and that the inhibition circuit is made active when the following conditions are simultaneously met:
For certain types of instructions that can be executed by the processor, a dependency potentially exists between the instruction that is ending and the next instruction capable of being executed in anticipation in a given unit. Such a dependency exists, for example, in the case where the next instruction is a conditional transfer of control instruction while the parameters enabling the calculation of the transfer of control conditioned for this instruction can be modified by one of the preceding instruction that have not yet been completed.
To solve this problem, and in another aspect of the invention, the processor is characterized in that the addressing unit includes dependency detection circuits furnishing a dependency signal when the instruction in standby must use information capable of being modified by an instruction that has not yet been completed in at least one of the units other than the addressing unit; that the dependency signal conditions the activation of the inhibition circuit; and that the activation of the inhibition circuit is cancelled when the dependency signal disappears.